There are several types of non-volatile memories, i.e. memories that retain memorized information in the absence of electrical power, able to be written and/or erased electrically:                EPROMs (“Erasable Programmable Read Only Memories”), of which the content can be written electrically, but which must be subjected to UV radiation to erase the memorized information;        EEPROMs (“Electrically Erasable Programmable ROMs”), of which the content can be written and erased electrically, but which require, in order to create them, semiconductor surfaces that are more substantial than memories of the EPROM type, and which therefore are more expensive to create.        
Non-volatile memories also exist, called Flash memories, which do not have the disadvantages of EPROM or EEPROM memories mentioned hereinabove. Indeed, a Flash memory is formed from a plurality of memory cells that can be programmed electrically individually, a large number of cells, called a block, sector or page, being able to be erased simultaneously and electrically. The Flash memories combine both the advantage of EPROM memories in terms of integration density and the advantage of EEPROM memories in terms of electrical erasing.
In addition, the durability and the low electrical consumption of Flash memories make them interesting for many applications: digital photo devices, mobile telephones, printers, personal assistants, portable computers, or portable audio playing and recording devices, USB keys, etc. In addition, Flash memories do not have any mechanical elements, which provide them with rather high resistance to impacts.
Most Flash memories are of the “stand-alone” type and have large storage capacities, generally greater than 1 Gb, and are dedicated to mass storage applications.
However, there are also Flash memories referred to as on-board (“embedded memories”) of which the creation is integrated into a method of the CMOS type and which has a growing interest, for example in the fields of the automobile or microcontrollers, for the storage of data or codes. These on-board Flash memories are created on a chip that further comprises CMOS devices intended to carry out logic functions other than memorization of data. These on-board Flash memories are generally made for storage capacities that are lower than those of the “stand-alone” type memories, with their capacities able to vary generally from a few bytes to a few Mb. The intended characteristics of on-board Flash memories are a low cost to produce them, excellent reliability (in particular at high temperature), low electrical consumption, or a high programming speed, with these characteristics being according to the application to which they are intended.
Most Flash memories comprise a structure of the MOS transistor type (gate, source, drain and channel) comprising a site for storing electrical charges, called a floating gate, formed for example from a layer of polysilicon arranged between two layers of oxide, and arranged between the electrically conductive gate material and the channel of the transistor. Memorization is carried out by applying on the conductive material a voltage greater than the threshold voltage, for example between 15 V and 20 V, which makes it possible to store the information in the form of charges trapped in the floating gate.
However, such memories have disadvantages that limit the reduction of their dimensions. Indeed, a reduction in the thickness of the tunnel oxide (oxide arranged between the channel and the layer of polysilicon) causes an increase in the SILC (“Stress Induced Leakage Current”). However, the prolonged use of such a memory (repetition of writing—erasing cycles) generates defects in the tunnel oxide which will assist the conduction of charges and degrade the retaining of the charges in the floating gate, which causes problems in the case of a substantial SILC. In practice, it is therefore difficult to reduce the thickness of the tunnel oxide of these memories to less than 8 nm without the SILC becoming a critical phenomenon for the memorization. In addition, by reducing the dimensions of such a memory cell, the cross-coupling between the floating gates of two adjacent cells of the same memory becomes substantial and can therefore degrade the reliability of the memory.
For these reasons, memories of the MONOS (Metal Oxide Nitride Oxide Silicon) type, also called NROM memories, have been proposed to replace the floating-gate memories made of polysilicon. Document U.S. Pat. No. 5,768,192 describes such memories wherein the electrical charges are stored in traps formed in a floating gate comprised of nitride and arranged between two layers of oxide. In such a layer of nitride, the traps are insulated from one another. As such, an electron stored in one of the traps remains physically located in this trap, which makes these memories much more “resistant” to the defects in the tunnel oxide, and therefore less impacted by an increase in the SILC. Indeed, in the presence of a defect in the tunnel oxide, the layer of memorization, i.e. the layer of nitride, loses only the electrons located in the close surroundings of the defect, with the other trapped electrons not being affected by this defect. These memories therefore have better reliability. It is as such possible to have a tunnel oxide with a thickness less than 8 nm, and therefore to reduce the required programming voltages. In addition, due to the low thickness of the nitride to form the memory layer, the coupling between two adjacent memory cells is greatly reduced in relation to floating-gate cells made of polysilicon. Finally, the structure of a memory of the NROM type is also adapted to carry out on-board memories due to the simplicity of the method for integrating these memories.
The document of S. Kianian and al., “A novel 3 volts-only, small sector erase, high density flash E2PROM” (Technical Digest of VLSI Technology, 1994, p. 71) describes another type of memory, called “split-gate” memory, which comprises within the same memory cell a memory transistor and a selection transistor (or control transistor) formed on a single active zone. Such a double-gate memory cell is generally programmed via source side injection, a mechanism that precisely requires the presence of a selection transistor placed alongside the memory transistor, and which makes it possible to increase the programming speed while still reducing the consumption in relation to a memory of the NROM type.
In order to benefit from the advantages of each structure, split-gate and NROM, document US2004/207025A1 proposes another type of double-gate memory that combines the structure of a memory of the NROM type with a split-gate architecture. One of the difficulties in carrying out these memories relates to controlling the position of the gates (gate of the control transistor and gate of the memory transistor) in relation to one another.
Indeed, these gates are carried out by two successive photolithographies, with the misalignment of the second gate in relation to the first gate setting the length of the second gate. Poor control of the relative positions of the two gates therefore results in poor control of the electrical characteristics of the second transistor, and therefore potentially poor performance of the memory. Consequently, a very precise control of the position of the gates is required during the creation of this type of memory.
In order to overcome this aligning constraint, document U.S. Pat. No. 7,130,223B2 proposes to carry out a double-gate memory that combines the structure of a memory of the NROM type with a split-gate architecture and wherein the gate of the memory transistor, i.e. the gate comprising the data memorization layer, is carried out in the form of a lateral spacer of the gate of the control transistor, arranged against one of the two lateral flanks of the gate of the control transistor. Such a structure makes it possible to precisely control the position and the dimension of the gate of the memory transistor in relation to the gate of the control transistor because, due to the fact that the gate of the memory transistor is carried out in the form of a lateral spacer, the latter is therefore self-aligned in relation to the gate of the control transistor.
Such a structure is shown in FIG. 1 which diagrammatically shows a double-gate memory 1 that combines the structure of a memory of the NROM type with a split-gate architecture wherein the gate of the memory transistor is carried out in the form of a lateral spacer of the gate of the control transistor. The memory 1 comprises an active zone 2 made in a semiconductor material and comprising a channel 3 arranged between a drain extension region 4 and a source extension region 5. The memory 1 further comprises a selection transistor gate 6 on top of a first portion 31 of the channel 3 and a memory transistor gate 7 arranged against the lateral flank of the gate of the selection transistor 6.
This memory transistor gate 7 comprises in particular:                a stack 10 of layers of which at least one of said layers is able to store electrical charges. The layer able to store electrical charges of said stack of layers can be arranged between two layers of dielectric material of said stack. The stack 10 can be for example of the ONO (oxide-nitride-oxide) type;        a conductive gate zone 11 of the memory transistor made of polysilicon having a substantially rounded lateral flank 15;        layers 12, 13 of thin spacers located on the rounded portion of the conductive zone 11, for example made of high thermal oxide (HTO) (layer 13) and of Si3N4 nitride (layer 12). These layers of thin spacers are also found on the opposite portion of the selection transistor.        
The stack 10 makes it possible to contribute to forming the gate of the memory transistor 7 and to contribute to insulating from one another the gate 6 of the selection transistor and the gate 7 of the memory transistor.
However, with such a structure, it is very difficult to then carry out an electrical contact on the gate of the memory transistor 7 in light of the small dimensions of this gate in the form of a lateral spacer. This carrying out of an electrical contact is for example illustrated by the silicidation zone 14 located at the top of the rounded lateral flank 15. It is observed that the zone allowing the silicidation is relatively reduced. This difficulty is further accentuated by the fact that the flanks obtained by the standard methods are rather of triangular shape; it is indeed very difficult to obtain by direct etching a rounded shape that makes it possible to obtain a sufficient silicidation surface. Such an architecture 16 is shown in FIG. 2. The memory 16 is identical to the memory 1 but has a conductive zone 17 of triangular shape whereon the silicidation zone 18 is even more limited than in the case of FIG. 1.
Moreover, the article “Scalability of split-gate charge memories down to 20 nm for low-power embedded memories” (Masoero and al.—Electron Devices Meeting (IEDM)—2011) demonstrated that reducing the memory gate length LMG (i.e. the length of the conductive gate zone 17 of the memory transistor closest to the channel 3 and measured according to the length of the channel 3—cf. FIG. 1) makes it possible to improve the electrical performance of the memory such as the programming window or the energy consumed. It is easily conceived that such a reduction in the gate length makes even more delicate the carrying out of a zone of substantial contact on the gate of the memory transistor.